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Freescale Semiconductor /MKM34Z7 /NVIC /NVIC_ISER

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Interpret as NVIC_ISER

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)SETENA0 0 (0)SETENA1 0 (0)SETENA2 0 (0)SETENA3 0 (0)SETENA4 0 (0)SETENA5 0 (0)SETENA6 0 (0)SETENA7 0 (0)SETENA8 0 (0)SETENA9 0 (0)SETENA10 0 (0)SETENA11 0 (0)SETENA12 0 (0)SETENA13 0 (0)SETENA14 0 (0)SETENA15 0 (0)SETENA16 0 (0)SETENA17 0 (0)SETENA18 0 (0)SETENA19 0 (0)SETENA20 0 (0)SETENA21 0 (0)SETENA22 0 (0)SETENA23 0 (0)SETENA24 0 (0)SETENA25 0 (0)SETENA26 0 (0)SETENA27 0 (0)SETENA28 0 (0)SETENA29 0 (0)SETENA30 0 (0)SETENA31

SETENA16=0, SETENA30=0, SETENA21=0, SETENA2=0, SETENA23=0, SETENA18=0, SETENA7=0, SETENA26=0, SETENA25=0, SETENA5=0, SETENA29=0, SETENA22=0, SETENA14=0, SETENA28=0, SETENA20=0, SETENA19=0, SETENA6=0, SETENA1=0, SETENA13=0, SETENA15=0, SETENA3=0, SETENA0=0, SETENA27=0, SETENA10=0, SETENA12=0, SETENA9=0, SETENA17=0, SETENA8=0, SETENA4=0, SETENA31=0, SETENA24=0, SETENA11=0

Description

Interrupt Set Enable Register

Fields

SETENA0

DMA channel 0 transfer complete interrupt set-enable bit

0 (0): write: no effect; read: DMA channel 0 transfer complete interrupt disabled

1 (1): write: enable DMA channel 0 transfer complete interrupt; read: DMA channel 0 transfer complete interrupt enabled
SETENA1

DMA channel 1 transfer complete interrupt set-enable bit

0 (0): write: no effect; read: DMA channel 1 transfer complete interrupt disabled

1 (1): write: enable DMA channel 1 transfer complete interrupt; read: DMA channel 1 transfer complete interrupt enabled
SETENA2

DMA channel 2 transfer complete interrupt set-enable bit

0 (0): write: no effect; read: DMA channel 2 transfer complete interrupt disabled

1 (1): write: enable DMA channel 2 transfer complete interrupt; read: DMA channel 2 transfer complete interrupt enabled
SETENA3

DMA channel 3 transfer complete interrupt set-enable bit

0 (0): write: no effect; read: DMA channel 3 transfer complete interrupt disabled

1 (1): write: enable DMA channel 3 transfer complete interrupt; read: DMA channel 3 transfer complete interrupt enabled
SETENA4

Serial Peripheral Interface 0/1 interrupt set-enable bit

0 (0): write: no effect; read: Serial Peripheral Interface 0/1 interrupt disabled

1 (1): write: enable Serial Peripheral Interface 0/1 interrupt; read: Serial Peripheral Interface 0/1 interrupt enabled
SETENA5

Programmable Delay Block 0 interrupt set-enable bit

0 (0): write: no effect; read: Programmable Delay Block 0 interrupt disabled

1 (1): write: enable Programmable Delay Block 0 interrupt; read: Programmable Delay Block 0 interrupt enabled
SETENA6

Low-voltage detect, low-voltage warning interrupt set-enable bit

0 (0): write: no effect; read: Low-voltage detect, low-voltage warning interrupt disabled

1 (1): write: enable Low-voltage detect, low-voltage warning interrupt; read: Low-voltage detect, low-voltage warning interrupt enabled
SETENA7

Quad Timer Channel 0 interrupt set-enable bit

0 (0): write: no effect; read: Quad Timer Channel 0 interrupt disabled

1 (1): write: enable Quad Timer Channel 0 interrupt; read: Quad Timer Channel 0 interrupt enabled
SETENA8

Quad Timer Channel 1 interrupt set-enable bit

0 (0): write: no effect; read: Quad Timer Channel 1 interrupt disabled

1 (1): write: enable Quad Timer Channel 1 interrupt; read: Quad Timer Channel 1 interrupt enabled
SETENA9

Quad Timer Channel 2 interrupt set-enable bit

0 (0): write: no effect; read: Quad Timer Channel 2 interrupt disabled

1 (1): write: enable Quad Timer Channel 2 interrupt; read: Quad Timer Channel 2 interrupt enabled
SETENA10

Quad Timer Channel 3 interrupt set-enable bit

0 (0): write: no effect; read: Quad Timer Channel 3 interrupt disabled

1 (1): write: enable Quad Timer Channel 3 interrupt; read: Quad Timer Channel 3 interrupt enabled
SETENA11

PIT0/PIT1 interrupt set-enable bit

0 (0): write: no effect; read: PIT0/PIT1 interrupt disabled

1 (1): write: enable PIT0/PIT1 interrupt; read: PIT0/PIT1 interrupt enabled
SETENA12

Low Leakage Wakeup interrupt set-enable bit

0 (0): write: no effect; read: Low Leakage Wakeup interrupt disabled

1 (1): write: enable Low Leakage Wakeup interrupt; read: Low Leakage Wakeup interrupt enabled
SETENA13

Command complete and read collision interrupt set-enable bit

0 (0): write: no effect; read: Command complete and read collision interrupt disabled

1 (1): write: enable Command complete and read collision interrupt; read: Command complete and read collision interrupt enabled
SETENA14

CMP0/CMP1/CMP2 interrupt set-enable bit

0 (0): write: no effect; read: CMP0/CMP1/CMP2 interrupt disabled

1 (1): write: enable CMP0/CMP1/CMP2 interrupt; read: CMP0/CMP1/CMP2 interrupt enabled
SETENA15

Segment LCD interrupt set-enable bit

0 (0): write: no effect; read: Segment LCD interrupt disabled

1 (1): write: enable Segment LCD interrupt; read: Segment LCD interrupt enabled
SETENA16

Analog-to-Digital Converter interrupt set-enable bit

0 (0): write: no effect; read: Analog-to-Digital Converter interrupt disabled

1 (1): write: enable Analog-to-Digital Converter interrupt; read: Analog-to-Digital Converter interrupt enabled
SETENA17

PORTA,PORTB,PORTC,PORTD,PORTE,PORTF,PORTH,PORTI,PORTJ,PORTK,PORTL,PORTM interrupt set-enable bit

0 (0): write: no effect; read: PORTA,PORTB,PORTC,PORTD,PORTE,PORTF,PORTH,PORTI,PORTJ,PORTK,PORTL,PORTM interrupt disabled

1 (1): write: enable PORTA,PORTB,PORTC,PORTD,PORTE,PORTF,PORTH,PORTI,PORTJ,PORTK,PORTL,PORTM interrupt; read: PORTA,PORTB,PORTC,PORTD,PORTE,PORTF,PORTH,PORTI,PORTJ,PORTK,PORTL,PORTM interrupt enabled
SETENA18

RNGA interrupt set-enable bit

0 (0): write: no effect; read: RNGA interrupt disabled

1 (1): write: enable RNGA interrupt; read: RNGA interrupt enabled
SETENA19

UART0/UART1/UART2/UART3 interrupt set-enable bit

0 (0): write: no effect; read: UART0/UART1/UART2/UART3 interrupt disabled

1 (1): write: enable UART0/UART1/UART2/UART3 interrupt; read: UART0/UART1/UART2/UART3 interrupt enabled
SETENA20

Memory Mapped Arithmetic Unit interrupt set-enable bit

0 (0): write: no effect; read: Memory Mapped Arithmetic Unit interrupt disabled

1 (1): write: enable Memory Mapped Arithmetic Unit interrupt; read: Memory Mapped Arithmetic Unit interrupt enabled
SETENA21

AFE Channel 0 interrupt set-enable bit

0 (0): write: no effect; read: AFE Channel 0 interrupt disabled

1 (1): write: enable AFE Channel 0 interrupt; read: AFE Channel 0 interrupt enabled
SETENA22

AFE Channel 1 interrupt set-enable bit

0 (0): write: no effect; read: AFE Channel 1 interrupt disabled

1 (1): write: enable AFE Channel 1 interrupt; read: AFE Channel 1 interrupt enabled
SETENA23

AFE Channel 2 interrupt set-enable bit

0 (0): write: no effect; read: AFE Channel 2 interrupt disabled

1 (1): write: enable AFE Channel 2 interrupt; read: AFE Channel 2 interrupt enabled
SETENA24

AFE Channel 3 interrupt set-enable bit

0 (0): write: no effect; read: AFE Channel 3 interrupt disabled

1 (1): write: enable AFE Channel 3 interrupt; read: AFE Channel 3 interrupt enabled
SETENA25

IRTC interrupt interrupt set-enable bit

0 (0): write: no effect; read: IRTC interrupt interrupt disabled

1 (1): write: enable IRTC interrupt interrupt; read: IRTC interrupt interrupt enabled
SETENA26

I2C0/I2C1 interrupt set-enable bit

0 (0): write: no effect; read: I2C0/I2C1 interrupt disabled

1 (1): write: enable I2C0/I2C1 interrupt; read: I2C0/I2C1 interrupt enabled
SETENA27

LPUART0 status and error interrupt set-enable bit

0 (0): write: no effect; read: LPUART0 status and error interrupt disabled

1 (1): write: enable LPUART0 status and error interrupt; read: LPUART0 status and error interrupt enabled
SETENA28

Multipurpose Clock Generator interrupt set-enable bit

0 (0): write: no effect; read: Multipurpose Clock Generator interrupt disabled

1 (1): write: enable Multipurpose Clock Generator interrupt; read: Multipurpose Clock Generator interrupt enabled
SETENA29

EWM/WDOG interrupt set-enable bit

0 (0): write: no effect; read: EWM/WDOG interrupt disabled

1 (1): write: enable EWM/WDOG interrupt; read: EWM/WDOG interrupt enabled
SETENA30

Low-Power Timer interrupt set-enable bit

0 (0): write: no effect; read: Low-Power Timer interrupt disabled

1 (1): write: enable Low-Power Timer interrupt; read: Low-Power Timer interrupt enabled
SETENA31

XBAR interrupt set-enable bit

0 (0): write: no effect; read: XBAR interrupt disabled

1 (1): write: enable XBAR interrupt; read: XBAR interrupt enabled

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data